In a recent design process of an integrated circuit, a designer describes the integrated circuit by using software in order to improve productivity. At an upstream phase of the design flow, the integrated circuit is described in a highly abstract behavioral level. A circuit data described in the behavioral level is referred to as a “behavioral level description file”. A behavioral synthesis system performs a behavioral synthesis of the behavioral level description file to automatically generate a circuit data described in a register transfer level (referred to as an “RT level description file”). Then, a logic synthesis of the RT level description file is performed at the downstream phase. By the logic synthesis, a circuit data described in a gate level is generated and an implementation design of a logic circuit is performed.
In the behavioral synthesis processing by the behavioral synthesis system, “scheduling” for mapping operations to clock cycles, “binding” for allocating the operations to functional units such as a multiplier and an adder, and the like are executed. Here, some scheduling modes are known with regard to the “scheduling” in the behavioral synthesis. According to David W. Knapp, “Behavioral Synthesis: Digital System Design Using the Synopsis Behavioral Compiler”, Prentice Hall, June 1999, pp. 57-60 (non-patent document 1), three scheduling modes: “cycle-fixed mode”, “superstate input-output mode” and “free-floating mode” are cited. Information of a clock cycle is included in the behavioral level description file, and it is possible to designate a cycle boundary between clock cycles. The above-mentioned scheduling modes define a relationship between the cycle boundaries and a relationship between the cycle boundary and input-output (I/O).
Modules and processes included in the modules are described in the behavioral level description file. The behavioral synthesis can be performed by switching the scheduling mode with respect to each process as a unit. However, a plurality of scheduling modes have not been applied to a single process. One reason for that is that the behavioral synthesis system terminates a cycle in response to the switching of scheduling engine and thus the number of cycles unnecessarily increases even when the behavioral synthesis is performed. Currently, a designer cannot designate a different scheduling mode only to an arbitrary block within a single process described in the behavioral level.